| MIPS ships multi-threaded 32-bit core family |
Feb. 06, 2006
MIPS Technologies is shipping a family of multi-threaded 32-bit RISC processor cores that it says can support multiple operating systems in SMP or AMP (symmetrical or asymmetrical multiprocessing) configurations. The "34K" family supports Linux, Windows CE, and other embedded OSes, and targets VoIP equipment, set-top boxes, network routers, digital TVs, digital cameras, portable media players, and other mobile handheld devices.
MIPS says its new 34K core family is the first to implement its "MT" (multi-threading) ASE (application-specific engine), which aims to harness processor cycles that might otherwise be spentidly awaiting memory fetches. The company claims that internal benchmarks have recorded a 60 percent performance increase, with only a 14 percent die size increase.
The 34K cores can be configured with a maximum of two VPEs (virtual processing elements). MIPS defines the term VPE as "a representation of the OS-only visible state of the MIPS32 architecture." Additionally, the cores support up to five TCs (thread contexts). TC is defined as "a representation of the user-state of the MIPS32 architecture." The diagram below clarifies these terms.
The 34K core usage model
MIPS says the 34K cores can run two independent OSes concurrently, or, alternatively, a single 2-way SMP OS, with support for up to five concurrently running process threads.
SMP OSes and applications require few modifications in order to run on 34K cores, MIPS says. Typical SMP applications include those requiring high performance, such as image processing, as well as those with "available explicit threads," such as devices that support multiple VoIP channels, the company says.
Alternatively, the 34K cores can support AMP OSes and applications, in which independent concurrent threads have different roles. AMP application examples include set-top boxes and networking devices, where control and signal plane processing can be done on a single processor, saving power, footprint, and expense, MIPS says.
Additionally, the 34K cores support the allocation of dedicated processing bandwidth to real-time tasks, MIPS says, guaranteeing QoS (quality of service). The cores' QoS mechanism tracks thread progress, taking measures as needed to ensure that real-time deadlines are met, the company adds.
MIPS says early customers using its 34K cores to build SoCs include Mobileye, iVivity, and PMC-Sierra. Early ecosystem partners include Accelerated Technology, Cadence, CoWare, Denali, Express Logic, First Silicon Solutions (FS2), Green Hills Software, Magma, Sonics, Synopsys, TimeSys, Virage Logic, and Virtio, it says.
Additionally, the 34K core supports tools interoperability specifications from the OCP-IP (Open Core Protocol International Partnership), which MIPS says "defines the high-performance, out-of-order, on-chip protocol that is employed in the native interface for all 34K cores."
Analyst Jim Turley, of Silicon Insider, stated, "MIPS has taken a straightforward and sensible approach in implementing multi-threading for embedded applications."
Availability
The 34K core family is available now, in 34Kc, 34Kf, 34Kc Pro, and 34Kf Pro models. Models with an "f" designation add an IEEE 754 hardware FPU (floating point unit), while those designated "Pro" add a CorExtend feature said to enable chip designers to integrate proprietary instructions and other tightly coupled hardware features.
The 34K cores will deliver 500MHz worst-case frequencies on 90nm process technology, according to MIPS, and have a core-only size of 2.1 square millimeters. Claimed core-only power consumption is 0.56 mW/MHz at 1 Volt.
MIPS supplies the 34K cores with a "Lite" version of its MIPS SDE (software development environment), a GNU tools-based toolset said to support the 34K cores' latest features. Addtionally, commercial embedded Linux and tool-chain support is available from TimeSys, through its recently announced MIPS LinuxLink subscription program, MIPS says.
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