Intel samples die-shrinks of edge/access networking SoCs

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Oct. 19, 2004

Intel is sampling die-shrinks of two SoCs (system-on-chip) for access and edge networking equipment. The XScale IXP2325 and IXP2350 are built on 90nm technology, and target applications that use a single chip for both data plane and control plane processing, Intel says.

Linux distributor MontaVista announced a real-time Linux project last week that aims to make Linux suitable for data plane as well as control plane processing.

According to Intel, the two new IXP23xx family chips share the same hardware and software architecture as other chips in Intel's IXP2xxx line, which Intel launched in February of 2002. However, they are the first of Intel's network processors built on 90nm process technology, said to save space and power while enabling the chips to support line rates up to 2Gbps. The smaller die size also leaves more room for cache; both new chips include 512KB of on-chip L2 cache.

Both new IXP23xx chips include XScale cores implemented by Intel based on an ISA (instruction set architecture) licensed from ARM. The cores include 32KB each of instruction and data cache. The IXP2325 is available at 600MHz or 900MHz, while the IXP2350 will add a 1.2GHz version.

The IXP2325 integrates two "fully programmable multi-threaded micro-engines (MEv2s) with large control store memory for single chip packet forwarding and traffic management up to 2.5 giga-operations per second," Intel says. The IXP2350 integrates four MEv2s, to delivers a claimed 4.9 giga-operations per second.

IXP2350 (left) and IXP2325 (right) block diagrams
(Click either to enlarge)
Additional features and peripherals listed by Intel include:

Two unidirectional 32-bit media interfaces (Rx and Tx) programmable as SPI-3 or UTOPIA
Two Gigabit Ethernet and two 10/100 Ethernet MACs integrated
High-speed serial controller
Cryptography accelerator
Two DDR DRAM interfaces, including a 32-bit DDR300/ECC channel optimized for the XScale core and a 64-bit DDR300/ECC channel for the MEv2s
I/O coherency for Intel XScale core DRAM
QDR SRAM interface
Asynchronous control interface supports 8- or 16-bit slow port devices via 16-bit expansion bus
Hardware support for memory access queuing
JTAG support
Intel IXA SDK and hardware development platform
1752 ball FCBGA package measuring 42.5mm square

"Using the scalable Intel network processor architecture for several of our product lines provides substantial savings," said Samsung Telecom VP Youngky Kim.

Availability

The IXP23XX chips are sampling now, and will ultimately be priced between $84 to $142 in quantities of 10,000. Intel will also deliver a development board for the chips based on the AdvancedTCA standard, it says.

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