| ARM adds souped up memory interconnect to ARM11 IP library |
Jun. 07, 2004
ARM has added three products to its library of off-the-shelf intellectual property for processor development around the ARM11 core. The products together comprise a high-performance interconnect between the processor, cache, and system memory. They target use in consumer, wireless, and other devices.
The AXI System Components aim to improve the performance of ARM11 cores even when used with low cost, slow external memory, according to ARM. They use on-chip memory caches more efficiently, in order to address the widening gap between processor speed and DRAM speed, estimated to be increasing at 50 percent annually.
The new AXI System Components are part of ARM's PrimeCell library of re-usable soft IP macrocells. They are intended for use in ARM11-based processors using AXI (Advanced eXtensible Interface), a high performance version of AMBA, ARM's open standard, on-chip bus specification. The AMBA 3.0 AXI specification was developed with technical contribution and review by over 30 participating companies, according to ARM.
The three new AXI System Components comprise:- L220 PrimeCell AXI Level-2 Cache Controller -- The L220 PrimeCell AXI Level-2 Cache Controller increases system performance between 50 percent and 100 percent, according to ARM, by storing recently-used data in high-speed on chip memory. It decreases power consumption by reducing external memory accesses.
- PL300 PrimeCell AXI Configurable Interconnect -- The PL300 PrimeCell AXI Configurable Interconnect provides a multi-layer topology that guarantees the necessary bandwidth and low latency for connected IP blocks, according to ARM. Throughput is 1.6GBytes per master at 200MHz, with no limitation on the number of masters. It comes with an XML machine-readable specification that enables integration into Spirit standard-based EDA (electronic design automation) tools, according to ARM.
- PL340 PrimeCell AXI SDRAM Controller -- The PL340 PrimeCell AXI SDRAM Controller is the first memory controller based on the AXI backplane specification. It provides up to 1GByte/s of bandwidth with 32-bit DDR SDRAM, and supports a range of memory types, including Mobile-DDR, DDR, Mobile SDR, and SDR.
The Components support ARM11 processors including the ARM1156T2-S and ARM1176JZ-S, as well as the recently announced MPCore multiprocessor core. They support ARM's Intelligent Energy Manager (IEM) and other off-the-shelf ARM11 IP components.
"In general, the features of AXI technology, such as data bursting, provide a big performance benefit to more advanced, ARM core-based embedded systems. With the addition of these AXI System Components, especially the Level-2 Cache Controller, designers will realize another huge boost in performance for ARM11 family-based processors," said EEMBC President Markus Levy. "Using an MPEG4 decode benchmark, similar to the one recently released by EEMBC, ARM was able to demonstrate a 74 percent performance improvement using only a 128k Level-2 cache."
"AXI System Components unleash the full benefits of high-frequency processors by optimizing memory system performance," said ARM Marketing Director John Cornish.
Availability
The AXI System Components are available now for licensing on a royalty-free basis.
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