| MPC823e: PowerPC mobile computing system-on-chip |
[Vendor: Motorola SPS]
The MPC823e microprocessor is a high-integration system-on-chip device that combines the functions of a PowerPC microprocessor core, communication processor, and display controller within a single silicon component. The device can be used in a wide variety of electronic applications, especially in low-power, portable, image capture and personal communication devices.
Linux support for using the MPC823e in a wide range of embedded and appliance applications is available from various third-party sources.
Q: "How many components are necessary to run Linux on an MPC823e and talk to the internet?"
A: "You would need RAM, ROM, reset controller, clock source, and an Ethernet transceiver."
Architecture
The MPC823e microprocessor uses a dual-processor architecture design approach with large data and instruction caches to provide high-performance using a general-purpose RISC integer processor and a special-purpose 32-bit scalar RISC communication processor module. The peripherals are uniquely designed for communication requirements and can provide embedded signal processing functions for high speed digital communication, imaging, user interface enhancements, and other I/O support.
Basically, the MPC823e is comprised of four main modules that interface with the 32-bit internal bus:- Embedded PowerPC core
- System interface unit
- Communication processor module
- LCD controller
The communication processor module can perform embedded signal processing functions for image compression and decompression. It also supports seven serial channels -- two serial communication controllers, two serial management controllers, one I2C port, one USB channel, and one serial peripheral interface. An important advantage of this two-processor architecture for mobile applications is that it consumes less power than traditional architectures because the communication processor module frees the core from peripheral processing tasks like imaging and communication.
Summary of MPC823E Features- Embedded PowerPC core
- 75MHz CPU clock rate
- Dynamic data bus sizing
- Completely static design (0-75MHz)
- Communication Processor Module
- Interfaces to PowerPC core via 8K dual-port RAM
- Protocols supported by ROM or downloaded microcode and the hardware Serial Communication Controllers include, but are not limited to, the digital portions of:
- Ethernet/IEEE 802.3 (CS/CDMA)
- HDLC/SDLC and HDLC Bus
- AppleTalk
- Universal Asynchronous Receiver Transmitter (UART)
- Synchronous UART (USART)
- Totally transparent mode with/ without CRC
- Asynchronous HDLC
- IrDA version 1.1 serial infrared (SCC2 only)
- Basic Rate ISDN (BRI) in conjunction with serial management controller channels
- Primary Rate ISDN
- Four Baud Rate Generators
- Two Serial Communication Controllers (SCCs)
- Ethernet/IEEE 802.3 support -- 10Mbps, full-duplex operation
- GeoPort support
- HDLC Bus Implements an HDLC-Based Local Area Network
- Universal Asynchronous Receiver Transmitter
- Synchronous UART
- Serial Infrared (IrDA) supporting a Maximum of 4Mbps (SCC2 only)
- Totally transparent; frame-based, with optional CRC
- Maximum serial data rate of 35Mbps
- One dedicated high speed serial channel for the Universal Serial Bus (USB); supports USB host/slave modes at up to 12Mbps with 4 USB endpoints
- Two serial management Controllers (SMCs) with externally accessible pins
- One Serial Peripheral Interface (SPI) port
- One I2C port (I2C)
- Interrupts:
- Four 16-Bit or two 32-Bit general purpose timers
- Seven external interrupt request (IRQ) lines
- Memory controller
- Supports 8 memory banks
- Glueless interface to DRAM SIMMs, SRAM, EPROM, Flash, or SDRAM
- System Integration Unit
- Hardware bus monitor
- Spurious interrupt monitor
- Software watchdog timer (WDT)
- Periodic interrupt timer
- Low-Power stop mode
- Clock synthesizer
- PowerPC decrementer and timebase
- Real-time clock (RTC)
- Reset controller
- IEEE 1149.1 test access port (JTAG)
- Video Controller
- Supports digital NTSC/PAL Video encoders and Digital TFT
- Sequential RGB, 4:4:4, and 4:2:2 YCrCb (CCIR 601) digital component video formats
- CCIR-656 compatible 8-bit interface port
- Horizontal sync, vertical sync, field and Blanking timing generation with half-clock resolution and programmable polarity
- Supports interlace/noninterlace scanning methods
- Programmable display active area
- Programmable background color for inactive area
- Glueless interface for most digital video encoders
- Hardware Horizontal Scrolling
- Uses burst read DMA cycles for maximum bus performance
- Panel voltage control adjustments for contrast set with on-chip timers
- End-of-frame interrupt generation
- LCD Controller
- Supports Digital TFT and Passive LCD panels
- Horizontal sync, vertical sync, field and Blanking timing generation with half-clock resolution and programmable polarity
- 1-, 2-, or 4-bit per pixel grayscale mode using advanced Frame Rate Control (FRC) algorithm
- 4 or 8 bits per pixel color mode
- 4-, 8-, 9-, or 12-bit parallel output to LCD displays
- Programmable display active area
- Non-split or vertically-split screen support
- Uses burst read DMA cycles for maximum bus performance
- End of frame interrupt generation
- Data for splits: 2+2 or 4+4 parallel bits (x+x refers to x bits each for lower and upper screens in parallel)
- Built-in Color RAM with 256 12-bit entries
- Programmable wait time between lines and frames
- Panel voltage control adjustments for contrast set with on-chip timers
- Programmable polarity for all LCD interface signals
- Single-Socket PCMCIA-ATA Interface
- Master interface, Release 2.1 compliant
- Single PCMCIA Socket
- Power Management Modes
- Normal High
- Normal Low
- Doze
- Sleep
- Deep Sleep
- Power-down
- Misc.:
- 3.3V Operation with 5V TTL compatibility of general purpose I/O pins and 3.3V for all others I/O pins
- Packaged in a single 256-Pin plastic ball grid array (PBGA)
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